1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of semiconductor regions including enhanced dopant profiles formed by means of halo regions.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. For this purpose, substantially crystalline semiconductor regions with or without additional dopant materials are defined at specified substrate locations to act as “active” regions, that is, to act, at least temporarily, as conductive areas. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, MOS technology is currently one of the most promising approaches, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A transistor, irrespective of whether an N-channel transistor or a P-channel transistor or any other transistor architecture is considered, comprises so-called PN junctions that are formed by an interface of highly doped regions, such as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
In the case of a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel, due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and the increase of gate resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, entails a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the dimensions of transistors. One major problem in this respect is the development of enhanced photolithography and etch strategies to reliably and reproducibly create circuit elements of critical dimensions, such as the gate electrode of the transistors, for a new device generation. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability.
However, the reduction of the gate length is associated with a reduced controllability of the respective channel, thereby requiring pronounced lateral dopant profiles and dopant gradients, at least in the vicinity of the PN junctions. Therefore, so-called halo regions are usually formed by ion implantation in order to introduce a dopant species whose conductivity type corresponds to the conductivity type of the remaining channel and semiconductor region so as to “reinforce” the resulting PN junction dopant gradient after the formation of respective extension and deep drain and source regions. In this way, the threshold voltage of the transistor, which represents the voltage at which a conductive channel forms in the channel region, significantly determines the controllability of the channel, wherein a significant variance of the threshold voltage may be observed for reduced gate lengths. Hence, by providing an appropriate halo implantation region, the controllability of the channel may be enhanced, thereby also reducing the variance of the threshold voltage, which is also referred to as threshold roll off, and also reducing significant variations of transistor performance with a variation in gate length. With the ongoing shrinkage of the gate length, however, an efficient compensation for threshold variance by a halo implantation may result in a significant degree of counter-doping of the respective extension regions, in particular when very shallow and thus highly doped halo implantations are required, which may more efficiently reduce the threshold variance compared to deeper halo implantations, which may be provided with a reduced dopant concentration yet provide a less efficient compensation mechanism. Consequently, the channel controllability may be enhanced by reducing the thickness of the gate insulation layer, which may however be restricted by increased static leakage currents and the physical limits of well-approved insulating materials, such as silicon dioxide.
With reference to FIGS. 1a-1c, the problems involved in the formation of conventional transistor devices will be described in more detail. FIG. 1a schematically illustrates in a cross-sectional view a first transistor element 100S, which may receive a shallow halo implantation, and a second transistor element 100D for receiving a moderately deep implantation. The first and second transistors 100S, 100D may comprise respective gate electrodes 104 that are formed above a channel region 103 provided in a semiconductor material 102, such as a silicon layer, which in turn is formed above a substrate 101. The gate electrode 104, which may have formed on sidewalls thereof a spacer element 107, is separated from the channel region 103 by a gate insulation layer 105. It may be assumed that the transistors 100S, 100D may have substantially the same configuration with respect to the components described so far. Moreover, the transistor 100S may be subjected to an ion implantation process 108S for forming in the semiconductor layer 102 respective halo regions 106S, which may be considered as shallow halo regions, which may be highly efficient in enhancing the controllability of the channel forming in the channel region 103 during operation of a device 100S. Thus, the implantation process 108S is performed with appropriate process parameters, such as implantation dose, energy and, as shown, tilt angle with respect to a direction substantially perpendicular to the layer 102, so as to obtain the implantation region 106S extending to a certain degree below the structure defined by the gate electrode 104 and the spacer 107, which acts as an implantation mask. It is to be noted that, however, a moderately high implantation dose and thus dopant concentration in the shallow region 106S is required in order to provide the efficient compensating mechanism for reducing short channel effects, such as reduced threshold roll off, to obtain enhanced channel controllability. On the other hand, the second transistor 100D is subjected to a halo implantation 108D, which is designed to provide a lower dopant concentration, thereby requiring a significantly greater depth so as to provide a moderately high compensation effect with respect to the threshold variance. It should be appreciated that a thickness of the gate insulation layer 105 may typically range from 1-3 nm and thus may not be significantly reduced on the basis of frequently used materials, such as silicon dioxide, silicon nitride and the like. The transistors 100S, 100D may be formed on the basis of well-established techniques, which include substantially the same processes for both transistors except for the halo implantations 108S, 108D.
FIG. 1b schematically shows the transistors 100S and 100D in a final manufacturing stage. Both transistors 100S, 100D may comprise an appropriate sidewall spacer structure 111, which may comprise a plurality of individual spacer elements and appropriate liner materials, depending on process and device requirements. Moreover, drain and source regions 110 connected to respective extension regions 109 may be formed within the semiconductor layer 102 adjacent to the channel region 103, wherein the extension regions 109 may form with the respective halo region 106S or 106D a PN junction, as is previously explained. Moreover, metal silicide regions 112 may be formed within the drain and source regions 110 and the gate electrode 104 in order to reduce the series resistance for connecting to the gate electrode 104 and the drain and source regions 110.
Typically, the transistors 100S, 100D may be formed by performing an appropriate implantation process for forming extension regions 109, possibly by providing an appropriate spacer element (not shown) or on the basis of the spacer 107, depending on the process and device requirements. Thereafter, the spacer structure 111 may be formed on the basis of well-approved techniques including the deposition of an appropriate material, such as silicon nitride, and a subsequent anisotropic etch process. Thereafter, a further implantation process may be performed in order to introduce dopant material for forming the deep drain and source regions 110. It should be noted that other implantation processes, as well as any intermediate anneal processes for activating respective dopant material, may also have been performed prior to the formation of the extension regions 109 and the drain and source regions 110 or may have been performed intermittently. After the completion of the respective implantation and anneal processes, thereby forming the PN junction between the extension region 109 and the halo regions 106S or 106D, the metal silicide regions 112 may be formed on the basis of any appropriate process technique, for instance involving the deposition of any appropriate refractory metal, such as cobalt, titanium, nickel, platinum or combinations thereof, with a subsequent heat treatment for forming a respective metal silicide.
FIG. 1c schematically illustrates the behavior of the transistors 100S, 100D with respect to a variation of threshold voltage with gate length, i.e., in FIGS. 1a and 1b the horizontal dimension of the gate electrodes 104, for otherwise identical configuration, wherein, as previously explained, a shallow halo implantation region, such as the region 106S, may provide a reduced variance of the threshold voltage for a decreasing gate length, as is indicated by the curve A in FIG. 1c. On the other hand, a moderately deep halo implantation region, such as the region 106D, may, for an otherwise identical transistor configuration, result in a significantly pronounced threshold roll off, thereby rendering this type of transistor less appropriate for sophisticated applications. Although the transistor 100S may be advantageous in view of its behavior with respect to the threshold roll off, the moderately high dopant concentration in the region 106S may, however, have a significant impact on the overall series resistance of the transistor 100S, thereby significantly reducing its current drive capability. That is, due to the moderately high dopant concentration in the halo implantation region 106S, a high degree of counter-doping is provided in the extension region 109, thereby reducing the conductivity thereof. Hence, a portion 109A between the metal silicide 112 and the channel region 103 may have an increased resistance compared to the respective region 109A of the transistor 100D, which has a significantly lower dopant concentration in the respective halo region 106D. Consequently, typical transistor configurations for advanced applications may represent a compromise between enhanced threshold roll off behavior with respect to drive current capability.
In view of the situation described above, there exists a need for an enhanced technique for forming transistor elements while avoiding one or more of the problems identified above or at least reducing the effects thereof.